1. Field of the Invention
The present invention relates to an inverter driving circuit for a liquid crystal display (LCD) backlight, more particularly, which is switched on/off more stably to improve heat radiation characteristics and drive efficiency.
2. Description of the Related Art
In general, a light crystal display (LCD) does not generate light on its own, thus requiring an additional backlight which adopts as a light source a fluorescent lamp or a light emitting diode.
The fluorescent lamp emits light due to electric discharge caused by a supply voltage applied to the fluorescent lamp. To keep discharging electricity, the fluorescent lamp should have an alternating current flowing therein. Therefore, the backlight requires an inverter for converting a direct current into an alternating current to provide the alternating current to the fluorescent lamp.
FIG. 1 is a block diagram illustrating a conventional LCD backlight inverter.
As shown in FIG. 1, a conventional liquid crystal display (LCD) includes a controller 1, a driver 2, a transformer 3, a backlight 4 and a feedback unit 5.
The controller 1 and the driver 2 constitute an inverter driving circuit for an LCD backlight. The driver 2 switches on/off a power supply of a direct current in response to a driving signal of the controller 1, and provides a first driving current to the transformer 3. The transformer 3 converts the first driving current into a second driving voltage to provide to the backlight 4, thereby allowing a fluorescent lamp of the backlight 4 to emit light.
The backlight 4 should provide a certain amount of light. To this end, the feed back unit 5 measures the second driving voltage to compare with a preset value, and provides a comparison result to the controller 1. In turn, the controller 1 alters the driving signal in response to the comparison result, thereby adjusting the amount of light to be uniform.
FIG. 2 is a block diagram illustrating a conventional inverter driving circuit for an LCD backlight. Referring to FIG. 2, the inverter driving circuit for the LCD backlight includes a controller 10, a level shifter 21, a first delay circuit 22, a second delay circuit 23, a power switching circuit 24. The controller 10 generates a first driving signal S1 of a square wave. The level shifter 21 boosts up and shifts the first driving signal S1 into a second driving signal S2 having a waveform and a phase identical to those of the first driving signal S1. The first delay circuit 22 delays a rising section of the first driving signal S1 and the second delay circuit 23 delays a falling section of the second driving signal S2. The power switching circuit 24 includes an N-channel field effect transistor (FET) 24a switched on/off by the first driving signal S3 delayed by the first delay circuit 22 and a P-channel FET 24b switched on/off by the second driving signal S4 delayed by the second delay circuit 23.
Operation of the conventional inverter driving circuit for the LCD will be described hereunder.
If the first driving signal S1 and the second driving signal S2 identical in waveform and phase are fed to the N-channel FET 24a and the P-channel FET 24b, respectively, ideally, the N-channel FET 24a and the P-channel FET 24b are switched on/off differentially from each other, thus not switched on simultaneously.
However, actually, at a point in time when levels of the first driving signal S1 and the second driving signal S2 are transited, the N-channel FET 24a and the P-channel FET 24bmay be turned on simultaneously. This may generate overcurrent, thereby potentially ruining the N-channel and P-channel FETs 24a and 24b. 
To prevent the FETs from being destroyed as described above, the first delay circuit 22 delays a rising section of the first driving signal S1 and provides the first driving signal S1 to the N-channel FET 24a. Also, the second delay circuit 23 delays a falling section of the second driving signal S2 and provides the second driving signal S2 to the P-channel FET 24b. This prevents the N-channel and P-channel FETs 24a and 24b from being turned on simultaneously.
On the other hand, a delay in rising sections of the first driving signal S1 and the second driving signal S2 will be described.
In the rising section of the first driving signal S1, the first delay circuit 22 has a first diode 22a reversely biased and current flows in a first resistor 22b. Accordingly, a resistor-capacitor (RC) circuit is formed by the first resistor 22b and an internal capacitor of the N-channel FET 24a. The first delay circuit 22 delays the first driving signal S1 by a delay time determined by a resistance of the first resistor 22b and a capacitance of the internal capacitor and provides a driving signal S3 to the N-channel FET 24a. 
In the rising section of the second driving signal S2, the second delay circuit 23 has a second diode 23a forwardly biased and current does not flow in the second resistor 23b, thus not delaying the second driving signal S2.
As a result, the P-channel FET 24b is turned off immediately from “ON” and the N-channel FET 24b is turned on after a predetermined time from “OFF”, thereby preventing the N-channel and P-channel FETs 24a and 24b from being turned on simultaneously.
In the meantime, an explanation will be given about the falling sections of the first and second driving signals S1 and S2.
In the falling section of the first driving signal S1, the first delay circuit 22 has the first diode 22a forwardly biased and the current does not flow in the first resistor 22b, thus not delaying the first driving signal S.
In the falling section of the second driving signal S2, the second delay circuit 23 has the second diode 23a reversely biased and the current flows in the second resistor 23b. Accordingly, an RC circuit is formed by the second resistor 23b and an internal capacitor of the P-channel FET 24b. The second delay circuit 23 delays the second driving signal S2 by a delay time determined by a resistance of the second resistor 23b and a capacitance of the internal capacitor and provides a driving signal S4 to the P-channel FET 24b. 
As a result, the N-channel FET 24a is turned off immediately from “ON” and the P-channel FET 24a is turned on after a predetermined time from “OFF”, thereby preventing the N-channel and P-channel FET 24a and 24b from being turned on simultaneously.
Here, the first diode 22a and the second diode 22b connected in parallel to the first and second resistors 22b and 23b, respectively, when driven forwardly, has an offset voltage of about 0.7V. The first diode 22a is driven forwardly when the first driving signal S1 is at a low level. Thus, the first driving signal S3 delayed by the first delay circuit 22 has a voltage of 0.7 V at a low level. Meanwhile, the second diode 23a is driven forwardly when the second driving signal S2 is at a high level. Thus, the second driving signal S4 delayed by the second delay circuit 23 has a voltage lower than an operating voltage by 0.7V at a high level.
FIG. 3 is a timing diagram illustrating a driving signal of the conventional inverter driving circuit for the LCD backlight.
As shown in FIG. 3, the first driving signal S1 and the second driving signal S2 are square waves having different voltage levels but identical waveforms and phases. The first delay circuit 22 delays the rising section of the first driving signal S1 by a preset time t1 and generates a delayed signal S3. Also, the second delay circuit 22 delays the falling section of the second driving signal S2 by a preset time t2 to generate a delayed signal S4.
The signal S3 has a relatively high voltage V1 of about 0.7V at a low level. On the other hand, the signal S3 has a relatively low voltage V2 that is 0.7V lower than the driving voltage Vcc at a high level. This may cause the N-channel FET 24a and the P-channel FET 24b to operate unstably.
Specifically, in a case where the signal S3 has a relatively high voltage V1 at a low level as described above, a voltage between a gate and a source of the N-channel FET 24a is equal to the voltage V1 and current flows between a drain and the source of the N-channel FET 24a, generating heat.
Moreover, in a case where the signal S4 has a relatively low voltage V2 than the driving voltage at a high level as described above, the voltage between a drain and a gate of the P-channel FET 24b is equal to the voltage V2 and current flows between the drain and a source of the P-channel FET 24b, generating heat.
As described above, heat may be generated by the voltages V1 and V2 in the N-channel and P-channel FETs 24a and 24b, thereby deteriorating overall drive efficiency.
Also, in a case where the first driving signal S1 is at a low level, the first diode 22a is forwardly biased. Here, electric charges in the internal capacitor of the N-channel FET 24a enter the controller 10 through the first diode 22b, disadvantageously heating the controller 10.